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| rev. f - 12 march, 2001 1 t87c5101 t83c5101/02 8-bit low pin count microcontrollers 1. description t8xc5101/02 family is a high performance cmos rom, otp, eprom derivative of the 80c51 cmos single chip 8-bit microcontroller. the t8xc5101/02 family is a low pin count device where only port 1, port 3 and 2/6 bits of a new port 4 are outputted. this prevents to do any external access, like external program memory access (fetch, movc) or external data memory (movx) the t8xc5101/02 family retains all features of the 80c51 with extended capacity 8kb rom (5102), 16kb rom (5101) / 16kb eprom/otp (5101) , 256 bytes of internal ram, a 6-source, 4-level interrupt system, an on-chip oscillator and three timer/counters. in addition, the t8xc5101/02 family has an xram of 256 bytes, the x2 feature, a more versatile serial channel that facilitates multiprocessor communication (euart), a dual data pointer and an improved timer 2. the fully static design of the t8xc5101/02 family allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the t8xc5101/02 family has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the timers, the serial port and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. 2. features 80c51 code compatible 8051 instruction compatible 16 i/o + 2 outputs in 24 pin packages 16 i/o + 6 outputs in 28 pin packages three 16-bit timer/counters 256 bytes scratchpad ram program memory 8kb rom t83c5102 16kb rom t83c5101 16kb eprom/otp t87c5101 high-speed architecture 40 mhz from 2.7 to 5.5v, commercial or industrial temperature range : - 40 mhz with a 40 mhz crystal in std mode - 40 mhz with a 20 mhz crystal in x2 mode 66 mhz from 4.5 to 5.5v, commercial temperature range - 40mhz with a 40 mhz crystal in std mode - 66mhz with a 33mhz crystal in x2 mode dual data pointer on-chip expanded ram (xram) (256 bytes) programmable clock out and up/down timer/ counter 2 asynchronous port reset interrupt structure with 6 interrupt sources, 4 level priority interrupt system full duplex enhanced uart framing error detection automatic address recognition low emi (no ale) power control modes idle mode power-down mode packages: so24, dil24, tssop24*, so28* * check for availability
2 rev. f - 12 march, 2001 t87c5101 t83c5101/02 3. block diagram timer 0 int ram 256x8 t0 t1 rxd txd v pp test xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core (2) (2) (2) (2) port 1 port 4 port 3 parallel i/o ports p1 p4 p3 xram 256x8 ib-bus reset prog vss vcc (2) (2) (1): alternate function of port 1 (2): alternate function of port 3 timer2 t2ex t2 (1) (1) rom /eprom 16kx8 (3) (3) (3): multiplexed function of port 4. rev. f - 12 march, 2001 3 t87c5101 t83c5101/02 4. sfr mapping the special function registers (sfrs) of the t8xc5101/02 fall into the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p1, p3, p4 timer registers: t2con, t2mod, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h serial i/o port registers: saddr, saden, sbuf, scon power and clock control registers: pcon interrupt system registers: ie, ip, iph others: auxr, ckcon no write must be made to reserved areas. reading a reserved area will give indeterminate result. table 1. all sfrs with their address and their reset value bit addressable non bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ffh f0h b 0000 0000 f7h e8h efh e0h acc 0000 0000 e7h d8h dfh d0h psw 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h p4 xx11 1111 c7h b8h ip xx00 000 saden 0000 0000 bfh b0h p3 1111 1111 iph xx00 0000 b7h a8h ie 0x00 0000 saddr 0000 0000 afh a0h auxr1 xxxx0xx0 a7h 98h scon 0000 0000 sbuf xxxx xxxx 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xxxxxx00 ckcon xxxx xxx0 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved 4 rev. f - 12 march, 2001 t87c5101 t83c5101/02 5. t8xc5101/02 pin configuration p4.1 / test p3.0 rst xtal2 xtal1 p3.1 1 vpp p4.0 / prog vss p1.6 p1.4 p1.5 p1.3 p1.1 / t2ex p1.0 / t2 p1.2 p3.4 / t0 p3.2 / int0 p3.3 / int1 vcc p3.5 / t1 p3.6 p3.7 p1.7 dil24 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ssop24* * check for availability so24 p4.1 / test p3.0 rst xtal2 xtal1 p3.1 1 vpp p4.0 / prog vss p1.6 p1.4 p1.5 p1.3 p1.1 / t2ex p1.0 / t2 p1.2 p3.4 / t0 p3.2 / int0 p3.3 / int1 vcc p3.5 / t1 p3.6 p3.7 p1.7 2 3 4 5 6 8 9 10 11 12 13 28 27 26 25 24 23 21 20 19 18 17 16 * check for availability so28* p4.3 7 p4.4 14 15 p4.5 p4.2 22 rev. f - 12 march, 2001 5 t87c5101 t83c5101/02 mnemonic pin number type name and function 24 pins 28 pins v ss 12 14 i ground: 0v reference v cc 24 28 i power supply: this is the power supply voltage for normal, idle and power- down operation p1.0-p1.7 13-20 15-20 22-23 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. port 1 also receives the low-order address byte during memory programming and verification. alternate functions for port 1 include: i/o t2 (p1.0): timer/counter 2 external count input/clockout i t2ex (p1.1): timer/counter 2 reload/capture/direction control p4.0 (prog)- p4.1 (test) 7 8 8 9 o (i) o (i) port 4 bits 0 & 1 : except during programming and verifying, these two bits are output port driving 30 micro amps at high level and sinking 10 ma at low level (vol < 1v). if they have 1s written to them, they output a high level and if they have 0 written to them, they output a low level. these 2 pins cannot be used as inputs. users should take care to never externally drive these pins low, especially during reset . these two pins are primarily designed to drive leds. during programming and verifying, these two pins are used as input, as explained in the corresponding chapter. a read or a read/modify/write instruction to these bits will read the status of the output: 1 if the output is 1, 0 if the output is 0. p4.2-p4.5 na 27 7 13 21 i/o port 4 bits 2 to 5: bidirectional i/o port with internal pull-ups. port 4.2 to 4.5 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 4.2 to 4.5 pins that are externally pulled low will source current because of the internal pull-ups. p3.0-p3.7 5-1 23-21 5-1 26-24 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 5 5 i rxd (p3.0): serial input port 4 4 o txd (p3.1): serial output port 33 i int0 (p3.2): external interrupt 0 22 i int1 (p3.3): external interrupt 1 11 i t0 (p3.4): timer 0 external input 23 26 i t1 (p3.5): timer 1 external input 22 25 i/o no alternate function on this pin 21 24 i/o no alternate function on this pin reset 9 10 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc. v pp 66 i programming supply voltage: this pin receives the 12.75v programming supply voltage (v pp ) during eprom programming. during normal operation, vpp pin must be tied to vcc. xtal1 11 12 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 10 11 o crystal 2: output from the inverting oscillator amplifier 6 rev. f - 12 march, 2001 t87c5101 t83c5101/02 6. low pin count specificities the t8xc5101/02 family is not able to perform any external memory access, such as a code fetch, a look-up table access (using movc) or a data access (using movx) because traditional port 0 and port 2 are not implemented anymore. it should be noted that 2 bits of a new port 4 are available, but they are pure user outputs. on the 28 pin package, there is also a set of 4 extra i/os, which cannot be used for external access. this inability to perform external memory accesses has the following consequences: port 0 sfr doesnt exist any more port 2 sfr doesnt exist any more port 4 has six bits defined among which two are pure outputs for led driving. security level 4 is no longer applicable code memory addresses is limited to 4000h. accessing to any address above 3fffh will return indeterminate value. jumps, subroutine calls, movc instructions should be limited to a maximum address range of 3fffh to avoid any error. external data memory addresses is limited to 100h. writing to any address above ffh will have no effect. reading any address above ffh will return indeterminate value. to avoid any mistake, movx address should be limited to a maximum address range of ffh. in rx devices, the user could disable the xram (for example, if he had shared resource at the corresponding address range). as no external access is possible with the t83/87c510x, it makes no sense to be able to disable accesses to xram. nevertheless, access to auxr bit 1 will cause no error and any write to this bit will have no effect. as there is no external access, ea, ale, psen, rd and wr signals are not implemented. so, the corresponding pins or alternate functions are removed. as there is no ale, there is no need for ale disabling. nevertheless, access to auxr bit 0 will cause no error and any write to this bit will have no effect. compared to the corresponding 16 kbyte rx2 device, the ts80c51rb2, the following features are removed: port 0 & 2 pca watchdog once mode power off flag (pof) rev. f - 12 march, 2001 7 t87c5101 t83c5101/02 7. t8xc5101/02 enhanced features in comparison to the original 80c52, the t8xc5101/02 implements some new features, which are : the x2 option. the dual data pointer. the extended ram. the 4 level interrupt priority system. some enhanced features are also located in the uart and the timer 2. 7.1. x2 feature the t8xc5101/02 core needs only 6 clock periods per machine cycle. this feature called x2 provides the following advantages: divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. save power consumption while keeping same cpu power (oscillator power saving). save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by software. 7.1.1. description the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 1. shows the clock generation block diagram. x2 bit is validated on xtal1 ? 2 rising edge to avoid glitches when switching from x2 to std mode. figure 2. shows the mode switching waveforms. figure 1. clock generation diagram xtal1 2 ckcon reg x2 state machine: 6 clock cycles. cpu control f osc f xtal 0 1 xtal1:2 8 rev. f - 12 march, 2001 t87c5101 t83c5101/02 figure 2. mode switching waveforms the x2 bit in the ckcon register (see table 2.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode). caution in order to prevent any incorrect operation while operating in x2 mode, user must be aware that all peripherals using clock frequency as time reference (uart, timers, pca...) will have their time reference divided by two. for example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. uart with 4800 baud rate will have 9600 baud rate. for further details on the x2 feature, please refer to anm072 available on the web (http://www.atmel-wm.com) xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode rev. f - 12 march, 2001 9 t87c5101 t83c5101/02 table 2. ckcon register ckcon - clock control register (8fh) reset value = xxxx xxx0b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - - x2 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 x2 cpu and peripheral clock bit clear to select 12 clock periods per machine cycle (std mode, f osc =f xtal / 2). set to select 6 clock periods per machine cycle (x2 mode, f osc =f xtal ). 10 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.2. dual data pointer register ddptr the additional data pointer can be used to speed up code execution and reduce code size in a number of ways. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 3.) that allows the program code to switch between them (refer to figure 3). figure 3. use of dual pointer table 3. auxr1: auxiliary register 1 auxr1 address 0a2h - - - - gf3 0 - dps reset value x x x x 0 0 x 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new feature. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. b. gf3 will not be available on first version of the rc devices. dps data pointer selection. dps operating mode 0 dptr0 selected 1 dptr1 selected gf3 this bit is a general purpose user flag b . external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 (on chip xram) rev. f - 12 march, 2001 11 t87c5101 t83c5101/02 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a source pointer and the other one as a "destination" pointer. 12 rev. f - 12 march, 2001 t87c5101 t83c5101/02 assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000 mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6 jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state. rev. f - 12 march, 2001 13 t87c5101 t83c5101/02 7.3. expanded ram (xram) the t8xc5101/02 provide 256 additional bytes of random access memory (ram) space for increased data parameter handling and high level language usage. the t8xc5101/02 have internal data memory that is mapped into four separate segments. the four segments are: ? 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. ? 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. ? 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. ? 4. the expanded ram bytes are indirectly accessed by movx instructions. as external accesses are not possible on the t8xc5101/02 family , it makes no sense to have the possibility to disable accesses to xram. thats why, compared to ts80c51rb2, writin ga1in auxr register bit 1 will have no effect, and wont disable access to the xram. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h, # data , accesses the sfr at location 0b0h (which is p3). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0b0h, accesses the data byte at address 0b0h, rather than p3 (which address is 0b0h). the 256 xram bytes can be accessed by indirect addressing, with movx instructions. this part of memory which is physically located on-chip, logically occupies the first 256 bytes of external data memory. the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to xram will not affect any ports . a write to external data memory locations higher than ffh (i.e. 0100h to ffffh) will have no effect. a read will return an indeterminate value. the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the xram. 14 rev. f - 12 march, 2001 t87c5101 t83c5101/02 figure 4. internal and external data memory address table 4. auxiliary register auxr auxr address 08eh - - - - - - extra m ao reset value x x x x x x 0 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ao writing to this bit will have no effect (refer to chapter "reduced emi mode") extram writing to this bit will have no effect xram 256 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function register 80 80 00 ff ff 00 ff indirect accesses direct accesses direct or indirect accesses rev. f - 12 march, 2001 15 t87c5101 t83c5101/02 7.4. timer 2 the timer 2 in the t8xc5101/02 family is compatible with the timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2, connected in cascade. it is controlled by t2con register (see table 5) and t2mod register (see table 6). timer 2 operation is similar to timer 0 and timer 1. c/ t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, autoreload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/ rl2 (t2con), as described in the atmel wireless & microcontrollers 8- bit microcontroller hardware description. refer to the atmel wireless & microcontrollers 8-bit microcontroller hardware description for the description of capture and baud rate generator modes. in t8xc5101/02 timer 2 includes the following enhancements: auto-reload mode with up or down counter programmable clock-output 7.4.1. auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the atmel wireless & microcontrollers 8-bit microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 5. in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution. 16 rev. f - 12 march, 2001 t87c5101 t83c5101/02 figure 5. auto-reload mode up/down counter (dcen = 1) 7.4.2. programmable clock-output in the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (see figure 6) . the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers : for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4) in x1 mode. the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: set t2oe bit in t2mod register. clear c/ t2 bit in t2con register. determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or a different one depending on the application. to start the timer, set tr2 run control bit in t2con register. (down counting reload value) c/ t2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt xtal1 : 12 f osc f xtal 0 1 t2conreg t2conreg t2conreg t2conreg t2ex: if dcen=1, 1=up if dcen=1, 0=down if dcen = 0, up counting (:6 in x2 mode) clock outfrequency C f osc 2 x 2 4 65536 rcap 2 h C rcap 2 l () -------------------------------------------------------------------------------------- = rev. f - 12 march, 2001 17 t87c5101 t83c5101/02 it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 6. clock-out mode c/ t2=0 :2 exf2 tr2 overflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 xtal1 t2con reg t2con reg t2con reg t2mod reg interrupt qd toggle exen2 (:1 in x2 mode) 18 rev. f - 12 march, 2001 t87c5101 t83c5101/02 table 5. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 over?ow flag must be cleared by software. set by hardware on timer 2 over?ow, if rclk = 0 and tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesnt cause an interrupt in up/down counter mode (dcen = 1) 5 rclk receive clock bit clear to use timer 1 over?ow as receive clock for serial port in mode 1 or 3. set to use timer 2 over?ow as receive clock for serial port in mode 1 or 3. 4 tclk transmit clock bit clear to use timer 1 over?ow as transmit clock for serial port in mode 1 or 3. set to use timer 2 over?ow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 over?ow. clear to auto-reload on timer 2 over?ows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1. rev. f - 12 march, 2001 19 t87c5101 t83c5101/02 table 6. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter. 20 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.5. t8xc5101/02 serial i/o port the serial i/o port in the t8xc5101/02 family is compatible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates. serial i/o port includes the following enhancements: framing error detection automatic address recognition 7.5.1. framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 7). figure 7. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 7.) bit is set. ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon (98h) pcon (87h) rev. f - 12 march, 2001 21 t87c5101 t83c5101/02 software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 8. and figure 9.). figure 8. uart timings in mode 1 figure 9. uart timings in modes 2 and 3 7.5.2. automatic address recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1 22 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.5.3. given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains dont-care bits (defined by zeros) to form the devices given address. the dont-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr 0101 0110b saden 1111 1100b given 0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a: saddr 1111 0001b saden 1111 1010b given 1111 0x0xb slave b: saddr 1111 0011b saden 1111 1001b given 1111 0xx1b slave c: saddr 1111 0010b saden 1111 1101b given 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a dont-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a dont care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 7.5.4. broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as dont-care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast =saddr or saden 1111 111xb the use of dont-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a: saddr 1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b: saddr 1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c: saddr= 1111 0010b saden 1111 1101b broadcast 1111 1111b for slaves a and b, bit 2 is a dont care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. rev. f - 12 march, 2001 23 t87c5101 t83c5101/02 7.5.5. reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all dont-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. saden - slave address mask register (b9h) reset value = 0000 0000b not bit addressable saddr - slave address register (a9h) reset value = 0000 0000b not bit addressable 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 24 rev. f - 12 march, 2001 t87c5101 t83c5101/02 table 7. scon register scon - serial control register (98h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6 sm1 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f xtal /12 (/6 in x2 mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f xtal /64 or f xtal /32 (/32, /16in x2 mode) 1 1 3 9-bit uart variable 5 sm2 serial port mode 2 bit / multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8 transmitter bit 8 / ninth bit to transmit in modes 2 and 3. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8 receiver bit 8 / ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti transmit interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri receive interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 8. and figure 9. in the other modes. rev. f - 12 march, 2001 25 t87c5101 t83c5101/02 table 8. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesnt affect the value of this bit. 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode. 26 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.6. interrupt system the t8xc5101/02 family has a total of 6 interrupt vectors: two external interrupts ( int0 and int1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. these interrupts are shown in figure 10. the addresses of the interrupt vectors are the same as in the standard c52. figure 10. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (see table 10.). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (see table 11.) and in the interrupt priority high register (see table 12.). shows the bit values and priority levels associated with each combination. table 9. priority level bit values iph.x ip.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest) ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 rev. f - 12 march, 2001 27 t87c5101 t83c5101/02 a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cant be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 10. ie register ie - interrupt enable register (a8h) reset value = 0x00 0000b bit addressable 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 et2 timer 2 over?ow interrupt enable bit clear to disable timer 2 over?ow interrupt. set to enable timer 2 over?ow interrupt. 4 es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 over?ow interrupt enable bit clear to disable timer 1 over?ow interrupt. set to enable timer 1 over?ow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 over?ow interrupt enable bit clear to disable timer 0 over?ow interrupt. set to enable timer 0 over?ow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0. 28 rev. f - 12 march, 2001 t87c5101 t83c5101/02 table 11. ip register ip - interrupt priority register (b8h) reset value = xx00 0000b bit addressable 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 pt2 timer 2 over?ow interrupt priority bit refer to pt2h for priority level. 4 ps serial port priority bit refer to psh for priority level. 3 pt1 timer 1 over?ow interrupt priority bit refer to pt1h for priority level. 2 px1 external interrupt 1 priority bit refer to px1h for priority level. 1 pt0 timer 0 over?ow interrupt priority bit refer to pt0h for priority level. 0 px0 external interrupt 0 priority bit refer to px0h for priority level. rev. f - 12 march, 2001 29 t87c5101 t83c5101/02 table 12. iph register iph - interrupt priority high register (b7h) reset value = xx00 0000b not bit addressable 7 6 5 4 3 2 1 0 - - pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 pt2h timer 2 over?ow interrupt priority high bit pt2h pt2 priority le v el 0 0 lowest 01 10 1 1 highest 4 psh serial port priority high bit psh ps priority le v el 0 0 lowest 01 10 1 1 highest 3 pt1h timer 1 over?ow interrupt priority high bit pt1h pt1 priority le v el 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1 priority le v el 0 0 lowest 01 10 1 1 highest 1 pt0h timer 0 over?ow interrupt priority high bit pt0h pt0 priority le v el 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0 priority le v el 0 0 lowest 01 10 1 1 highest 30 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.7. idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirely : the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occured during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 7.8. power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 8., pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power-down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 11. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put t8xc5101/02 into power-down mode. figure 11. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase rev. f - 12 march, 2001 31 t87c5101 t83c5101/02 table 13. the state of ports during idle and power-down modes mode program memory port1 port3 port4 idle internal port data port data port data power down internal port data port data port data 32 rev. f - 12 march, 2001 t87c5101 t83c5101/02 7.9. reduced emi mode as there is no port 0 nor port 2 outputted from this device, there is no need to output ale. emi are then reduced intrinsically. the bit which controls ale disabling in rx devices is a0 (bit 0) in register auxr. as explained earlier for bit extram, writing any value to ao will have no effect on the device behavior. table 14. auxr register auxr - auxiliary register (8eh) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - extram ao bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 extram extram bit writing to this bit will have no effect. the value read from this bit is indeterminate. 0 ao ale output bit writing to this bit will have no effect. the value read from this bit is indeterminate. rev. f - 12 march, 2001 33 t87c5101 t83c5101/02 8. t83c5101/02 rom 8.1. rom structure the t83c5101/02 rom memory is divided in three different arrays: the code array t83c5101: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kbytes. t83c5102: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 kbytes. the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 8.2. rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 8.2.1. encryption array within the rom array are 64 bytes of encryption array. every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. 8.2.2. program lock bits the lock bits when programmed according to table 15. will provide different level of protection for the on-chip code and data. u: unprogrammed p: programmed 8.2.3. signature bytes the t8xc5101/02 family contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in sections 9.3.2 and 9.5.1. 8.2.4. verify algorithm refer to section table 9.3.5 table 15. program lock bits program lock bits protection description security level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. 2 p u u not applicable as usually this protection deals with executing movc from external memory (impossible) and sampling ea pin (doesnt exist any more) 3 u p u verify disable. this security level is available because rom integrity will be veri?ed thanks to another method. 34 rev. f - 12 march, 2001 t87c5101 t83c5101/02 9. t87c5101 eprom 9.1. eprom structure the t87c5101 eprom is divided into two different arrays: the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kbytes. the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. in addition a third non programmable array is implemented: the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 9.2. eprom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 9.2.1. encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all ffs). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. 9.2.2. program lock bits the three lock bits, when programmed according to table 16., will provide different level of protection for the on-chip code and data. u: unprogrammed, p: programmed warning: security level 2 and higher should only be programmed after eprom verification. 9.2.3. signature bytes the t8xc5101/02 family contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section 9.3.2. and 9.5.1. . table 16. program lock bits program lock bits protection description security level lb1 lb2 lb3 1 u u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. 2 p u u further programming of the program memory is disabled. 3 u p u same as security level 2 + verify disabled. 4 u u p not applicable as usually this protection deals with external execution, which is impos- sible with this device. rev. f - 12 march, 2001 35 t87c5101 t83c5101/02 9.3. eprom programming 9.3.1. set-up modes in order to program and verify the eprom or to read the signature bytes, the t87c5101 is placed in specific test modes (see figure 12.). control and program signals must be held at the levels indicated in table 17. 9.3.2. definition of terms address and control lines: rst, test, port 3 data lines: port 1 program signals: vpp, prog table 17. eprom set-up modes na: not applicable figure 12. programming and verifying modes configuration mode rst test prog vpp p3.7 p3.6 p3.3 p3.2 p3.1 program code data 1 0/1 0/ 12.75v 1 1 1 1 0 verify code data 1 0/1 1 0/1 1 1 0 0 0 program encryption array address 0-3fh 1 0/1 0/ 12.75v 1 0 1 1 0 read signature bytes 1 0 1 0 0 0 0 0 0 program lock bit 1 1 0/1 0/ 12.75v 1 1 1 1 1 program lock bit 2 1 0/1 0/ 12.75v 0 0 1 1 1 program lock bit 3 na na na na na na na na na read lock bits 1 0 1 0 1 0 0 0 0 5v vcc rst vpp prog test tcode xtal1 1 4 to 12 mhz p1 p3 data 0 / 1 1 0 / 1 5v vcc rst vpp prog test tcode xtal1 1 0 / 1 / vpp 4 to 12 mhz p1 p3 data 0 / 1 programming configuration verifying configuration / adh / adl / adh / adl tcode = test code, adh = address high, adl = address low 36 rev. f - 12 march, 2001 t87c5101 t83c5101/02 9.3.3. eprom programming and verification characteristics t a =21 cto27 c; v ss = 0v; v cc =5v 10% while programming. v cc = operating range while verifying 9.3.4. programming algorithm step 1: vpp and test low, present t code for programming on p3 and raise vpp to 12.75v step 2: present address high on p3 and pulse test high step 3: present address low on p3 and data on p1 step 4: pulse prog low step 5: back to step 3 if the next byte to program is in the same 256 byte page or step 5: back to step 2 if the next byte to program is in a different page figure 13. programming signalswaveform table 18. eprom programming parameters symbol parameter min max units v pp programming supply voltage 12.5 13 v i pp programming supply current 75 ma 1/t clcl oscillator frequency 4 12 mhz tphdz tglgx tghdx tdvgx tghcx tcvgx ttlcx tcvtx tthtx tphtx tphcx tcvpx tcode prog adh#1 adl #1 adh#2 data #1 data #2 adl #2 data#3 adl#3 vpp test prog p3 p1 vpp=12.75v rev. f - 12 march, 2001 37 t87c5101 t83c5101/02 9.3.5. verifying algorithm step 1: vpp and test low, present t code for verification on p3 and raise vpp to vcc step 2: present address high and pulse test high step 3: present address low on p3 and read data on p1 step 4: back to step 3 if the next byte is in the same 256 byte page or step 4: back to step 2 if the next byte to program is in a different page 12 mhz symbol parameter formula min max unit tosc oscillator period - 83.3 ns tcvpx code input valid to vpp rising edge setup time 36 tosc 3 m s tphcx code input valid from vpp high hold time 1 tosc 83.3 ns tphtx test input valid from vpp high hold time 1 tosc 83.3 ns tthtx test high pulse width 36 tosc 3 m s tcvtx address high valid to test falling edge setup time 36 tosc 3 m s ttlcx address input valid from test falling edge hold time 1 tosc 83.3 ns tphdz data output hi-z from vpp high delay 0 tglgx prog low pulse width 90 110 m s tcvgx address valid to prog falling edge setup time 36 tosc 3 m s tdvgx data input valid to prog falling edge setup time 36 tosc 3 m s tghcx address valid from prog rising edge hold time 1 tosc 83.3 ns tghdx data input valid from prog rising edge hold time 1 tosc 83.3 ns 38 rev. f - 12 march, 2001 t87c5101 t83c5101/02 figure 14. verifying signalswaveform * adh is egal to 0 when addressing signature bytes 9.3.6. programming / verify algorithm step 1: vpp and test low, present t code for programming on p3 and raise vpp to 12.75v step 2: present address high on p3 and pulse test high step 3: present address low on p3 and data on p1 step 4: pulse prog low step 5: present t code for verifying on p3 and lower vpp to 0v step 6: read previous data step 7: present t code for programming on p3 and raise vpp to 12.75v step 8: goto step 3 if the next byte to program is in the same 256 byte page or step 8: goto step 2 if the next byte to program is in a different page 12 mhz symbol parameter formula min max unit tosc oscillator period 83.3 ns tcvpx code input valid to vpp rising edge setup time 36 tosc 3 m s tphcx code input valid from vpp high hold time 1 tosc 83.3 ns tphtx test input valid from vpp high hold time 1 tosc 83.3 ns tthtx test high pulse width 36 tosc 3 m s tcvtx address high valid to test falling edge setup time 36 tosc 3 m s ttlcx address input valid from test falling edge hold time 1 tosc 83.3 ns tcvdv address valid to data output valid delay 36 tosc 3 m s tcxdx data valid from address invalid hold time 0 tcxdx tcvdv ttlcx tcvtx tthtx tphtx tphcx tcvpx tcode adh#1* adl #1 adh#2* data #1 data #2 adl #2 data#3 adl#3 vpp test prog p3 p1 vpp high is 5v rev. f - 12 march, 2001 39 t87c5101 t83c5101/02 figure 15. programming / verifying signalswaveform note: after programming, addresses high and low are already latched in the device, and when switching to verify, the device outputs directly the last written data. 12 mhz symbol parameter formula min max unit tosc oscillator period - 83.3 ns tcvpx code input valid to vpp rising edge setup time 36 tosc 3 m s tphcx code input valid from vpp high hold time 1 tosc 83.3 ns tphtx test input valid from vpp high hold time 1 tosc 83.3 ns tthtx test high pulse width 36 tosc 3 m s tcvtx address high valid to test falling edge setup time 36 tosc 3 m s ttlcx address input valid from test falling edge hold time 1 tosc 83.3 ns tphdz data output hi-z from vpp high delay 0 tglgx prog low pulse width 90 110 m s tcvgx address valid to prog falling edge setup time 36 tosc 3 m s tdvgx data input valid to prog falling edge setup time 36 tosc 3 m s tghcx address valid from prog rising edge hold time 1 tosc 83.3 ns tghdx data input valid from prog high hold time 1 tosc 83.3 ns tghpx vpp on vpp pin from prog high hold time 36 tosc 3 m s ttxdx data output valid from t code invalid hold time 0 ttvdv data output valid from t code valid delay 36 tosc 3 m s tplcx address valid from vpp falling edge hold time 36 tosc 3 m s tppgx vpp on vpp pin to prog falling edge setup time 36 tosc 3 m s tpldx data output from vpp low delay 0 m s tplcx tphdz tglgx tghdx tghcx tdvgx tcvgx ttlcx tcvtx tthtx tppgx tcvpx tghpx tphtx tphcx tcode prog adh#1 adl#1 data#1 (in) tcode ver tcode prog adl#2 data#2 (in) vpp test prog p3 p1 vpp=12.75v data#1 (out) ttvdv ttxdx tpldx 40 rev. f - 12 march, 2001 t87c5101 t83c5101/02 9.3.7. lock bits programmation and verification 9.3.7.1. programmation : step 1: vpp and test low, present t code for lock bits programming on p3 and raise vpp to 12.75v step 2: pulse prog low 9.3.7.2. verification : step 1 : vpp and test low, present t code for lock bits verification step 2 : read data figure 16. lock bits programming signalswaveform and lock bits verifying signalswaveform ?vpp pin in driven : 12 mhz symbol parameter formula min max unit tosc oscillator period - 83.3 ns tcvpx code input valid to vpp rising edge setup time 36 tosc 3 m s tphcx code input valid from vpp high hold time 1 tosc 83.3 ns tppgx vpp on vpp pin to prog low setup time 36 tosc 3 m s tglgx prog low pulse width 90 110 m s tghpx vpp on vpp pin from prog high hold time 36 tosc 3 m s tpldv data output valid from vpp low delay 36 tosc 3 m s tpldx data output from vpp low delay 0 ttvdv data output valid from t code valid delay 36 tosc 3 m s ttxdx data output valid from t code invalid hold time 0 tphdz data output hi-z from vpp high delay 0 tplcv vpp low to t code valid setup time 36 tosc 3 m s tpldx tphdz tglgx tglgx tghpx tppgx tphcx tcvpx vpp test prog p3 p1 vpp=12.75v t code t code data out tpldv ttvdv ttxdx tplcv rev. f - 12 march, 2001 41 t87c5101 t83c5101/02 -to 0v when p3 contains the test code -to 5v when p3 contains high order or low order addresses -to vpp during programming cycled ?test pin is driven : -to 5v when p3 contains high order address -to 0v in the other cases 9.4. eprom erasure (windowed packages only) erasing the eprom erases the code array, the encryption array and the lock bits returning the parts to full functionality. erasure leaves all the eprom cells in a 1s state (ff). 9.4.1. erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ?) to an integrated dose at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. an exposure of 1 hour is recommended with most of standard erasers. erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 ?. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 9.5. signature bytes 9.5.1. signature bytes content the t8xc5101/02 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom verify but activate the control lines provided in table 17. for read signature bytes. table 19. shows the content of the signature byte for the t8xc5101/02. table 19. signature bytes content location contents comment 30h 58h manufacturer code: atmel wireless & microcontrollers 31h 57h family code: c51 x2 60h 3bh product name: t83c5101/02 8k or 16k rom version 60h bbh product name: t87c5101 16k otp version 61h efh product revision number : t8xc5101/02 rev.0 42 rev. f - 12 march, 2001 t87c5101 t83c5101/02 10. electrical characteristics 10.1. absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 cto70 c i = industrial -40 cto85 c storage temperature -65 cto+150 c voltage on v cc to v ss -0.5vto+7v voltage on v pp to v ss -0.5vto+13v voltage on any pin to v ss -0.5vtov cc + 0.5 v power dissipation 1 w (2) notes 1. s tresses at or above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is speci?cation is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package. 10.2. power consumption measurement since the introduction of the first c51 devices, every manufacturer made operating icc measurements under reset, which made sense for the designs were the cpu was running under reset. in atmel wireless & microcontrollers new devices, the cpu is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. thats why, while keeping measurements under reset, atmel wireless & microcontrollers presents a new way to measure the operating icc: using an internal test rom, the following code is executed: label: sjmp label (80 fe) ports 1, 3, 4 are disconnected, rst = vss, xtal2 is not connected and xtal1 is driven by the clock. this is much more representative of the real operating icc. rev. f - 12 march, 2001 43 t87c5101 t83c5101/02 10.3. dc parameters for standard voltage t a =0 cto+70 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. t a = -40 cto+85 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. table 20. dc parameters in standard voltage symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4.2-4.5 (6) 0.3 0.45 1.0 v v v i ol = 100 m a i ol = 1.6 ma i ol = 3.5 ma v ol1 output low voltage, port 4.0-4.1 (6) 0.76 (5) 0.5 1.0 v v v i ol = 10.0 ma i ol = 6.0 ma i ol = 12.0 ma v oh output high voltage, ports 1, 3, 4.2-4.5 (6) v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = -30 m a i oh = -60 m a v cc = 5 v 10% r rst rst pulldown resistor 50 90 (5) 200 k w i il logical 0 input current ports 1, 3 and 4 -50 tbd m a vin = 0.45 v, port 1 & 3 vin = 0.45 v, port 4 i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 3 -650 tbd m a vin = 2.0 v, port 1 & 3 vin = 2.0 v, port 4 c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current to be con- ?rmed 20 (5) 50 m a 2.0 v < v cc < 5.5 v (3) i cc under reset power supply current maximum values, x1 mode: (7) to be con- ?rmed 1 + 0.4 freq (mhz) @12mhz 5.8 @16mhz 7.4 ma v cc = 5.5 v (1) i cc operating power supply current maximum values, x1 mode: (7) to be con- ?rmed 3 + 0.6 freq (mhz) @12mhz 10.2 @16mhz 12.6 ma v cc = 5.5 v (8) i cc idle power supply current maximum values, x1 mode: (7) to be con- ?rmed 0.25+0.3freq (mhz) @12mhz 3.9 @16mhz 5.1 ma v cc = 5.5 v (2) 44 rev. f - 12 march, 2001 t87c5101 t83c5101/02 10.4. dc parameters for low voltage t a =0 cto+70 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. t a = -40 cto+85 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. table 21. dc parameters for low voltage notes 1. i cc under reset is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 21.), v il = v ss + 0.5 v, v ih = v cc - 0.5v; xtal2 n.c.; vpp = rst = v cc . i cc would be slightly higher if a crystal oscillator used. 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch ,t chcl = 5 ns, v il =v ss + 0.5 v, v ih =v cc - 0.5 v; xtal2 n.c; vpp = rst = v ss (see figure 19.). 3. power down i cc is measured with all output pins disconnected; vpp = v ss ; xtal2 nc.; rst = v ss (see figure 20). 4. not applicable 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4.2-4.5 (6) 0.45 v i ol = 0.8 ma v ol1 output low voltage, port 4.0-4.1 (6) 0.83 (5) 0.5 v v i ol = 10.0 ma i ol = 4.8 ma v oh output high voltage, ports 1, 3, 4.2-4.5 (6) 0.9 v cc v i oh = -10 m a i il logical 0 input current ports 1, 2 and 3 -50 tbd m a vin = 0.45 v, port 1 & 3 vin = 0.45 v, port 4 i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 3 -650 tbd m a vin = 2.0 v, port 1 & 3 vin = 2.0 v, port 4 r rst rst pulldown resistor 50 90 (5) 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current to be con- ?rmed 20 (5) 10 (5) 50 30 m a v cc = 2.0 v to 5.5 v (3) v cc = 2.0 v to 3.3 v (3) i cc under reset power supply current maximum values, x1 mode: (7) to be con- ?rmed 1 + 0.2 freq (mhz) @12mhz 3.4 @16mhz 4.2 ma v cc = 3.3 v (1) i cc operating power supply current maximum values, x1 mode: (7) to be con- ?rmed 1 + 0.3 freq (mhz) @12mhz 4.6 @16mhz 5.8 ma v cc = 3.3 v (8) i cc idle power supply current maximum values, x1 mode: (7) to be con- ?rmed 0.15 freq (mhz) + 0.2 @12mhz 2 @16mhz 2.6 ma v cc = 3.3 v (2) rev. f - 12 march, 2001 45 t87c5101 t83c5101/02 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 6 and 8-bit port: port 4.0 + 4.1: 20 ma port 4.2 to 4.5 : 8 ma ports 1 and 3: 15 ma maximum total i ol for all output pins: 58 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. 7. for other values, please contact your sales of?ce. 8. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 21.), v il = v ss + 0.5 v, v ih =v cc - 0.5v; xtal2 n.c.; vpp= v cc ; rst = v ss . the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillator is used. measurements are made with otp products when possible, which is the worst case. figure 17. i cc test condition, under reset vpp v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc 46 rev. f - 12 march, 2001 t87c5101 t83c5101/02 figure 18. operating i cc test condition figure 19. i cc test condition, idle mode figure 20. i cc test condition, power-down mode figure 21. clock signal waveform for i cc tests in active and idle modes vpp v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc reset = vss after a high pulse during at least 24 clock cycles rst vpp xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnected. clock signal reset = vss after a high pulse during at least 24 clock cycles rst vpp xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnected. reset = vss after a high pulse during at least 24 clock cycles v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns. rev. f - 12 march, 2001 47 t87c5101 t83c5101/02 10.5. ac parameters 10.5.1. explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example:t xhdv = time from clock rising edge to input data valid. t a =0to+70 c (commercial temperature range); v ss =0v;v cc =5v 10%; -v ranges. t a =0to+70 c (commercial temperature range); v ss =0v;2.7v rev. f - 12 march, 2001 49 t87c5101 t83c5101/02 10.5.3. shift register timing waveforms figure 22. shift register timing waveforms 10.5.4. external clock drive characteristics (xtal1) 10.5.5. external clock drive waveforms figure 23. external clock drive waveforms table 27. ac parameters symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid v cc -0.5 v 0.45 v 0.7v cc 0.2v cc -0.1 v t chcl t clcx t clcl t clch t chcx 50 rev. f - 12 march, 2001 t87c5101 t83c5101/02 10.5.6. ac testing input/output waveforms figure 24. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic 1 and 0.45v for a logic 0. timing measurement are made at v ih min for a logic 1 and v il max for a logic 0. 10.5.7. float waveforms figure 25. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 3 20ma. 10.5.8. clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by two. figure 26. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. 0.45 v v cc -0.5 v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1 v v oh -0.1 v float v load v load +0.1 v v load -0.1 v clock xtal2 internal state4 state5 state6 state1 state2 state3 state4 state5 serial por t shift clock por t opera tion txd (mode 0) rxd sampled rxd sampled p1, p3, p4 pins sampled p1, p3, p4 pins sampled mov dest port (p1, p3, p4) (includes int0, int1, to, t1) old data new data p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 rev. f - 12 march, 2001 51 t87c5101 t83c5101/02 11. ordering information table 28. maximum clock frequency code -v -l unit standard mode, oscillator frequency standard mode, internal frequency 40 40 40 40 mhz x2 mode, oscillator frequency x2 mode, internal equivalent frequency 33 66 20 40 mhz packages: td : so24 3z: dil24 cz: cdil24 window* ic : ssop24* ti: so28* t part number 87c5101 (16k eeprom/otp) 83c5101zzz (16k rom, zzz is the customer code) 83c5102zzz (8k rom, zzz is the customer code) conditioning s: stick r: tape & reel u: stick and dry pack f: tape & reel and dry pack r (*) check with atmel wireless & microcontrollers sales of?ce for availability 87c5101 -3z c temperature range c: commercial 0 to 70 o c i: industrial -40 to 85 o c e: engineering samples v: vcc: 5v +/- 10% 40 mhz, x1 mode 33 mhz, x2 mode l: vcc: 2.7 to 5.5 v 40 mhz, x1 mode 20 mhz, x2 mode v 52 rev. f - 12 march, 2001 t87c5101 t83c5101/02 table 29. possible order entries exten- sion type t83c5101 t83c5102 mask rom t87c5101 otp -3zscl dil24, stick, comm. 2.7-5.5v, 40 mhz x x -3zscv dil24, stick, comm. 5v, 66mhz x x -3zsil dil24, stick, ind. 2.7-5.5v, 40 mhz x x -tdscl so24, stick, comm. 2.7-5.5v, 40 mhz x x -tdscv so24, stick, comm. 5v, 66mhz x x -tdsil so24, stick, ind. 2.7-5.5v, 40 mhz x x -tdrcl so24, tape & reel, comm. 2.7-5.5v, 40 mhz x x -tdrcv so24, tape & reel, comm. 5v, 66mhz x x -tdril so24, tape & reel, ind. 2.7-5.5v, 40 mhz x x -tiscl so28, stick, comm. 2.7-5.5v, 40 mhz x x -tiscv so28, stick, comm. 5v, 66mhz x x -tisil so28, stick, ind. 2.7-5.5v, 40 mhz x x -tircl so28, tape & reel, comm. 2.7-5.5v, 40 mhz x x -tircv so28, tape & reel, comm. 5v, 66mhz x x -tiril so28, tape & reel, ind. 2.7-5.5v, 40 mhz x x -icucl ssop24, stick & dry pack, comm. 2.7-5.5v, 40 mhz x x -icucv ssop24, stick & dry pack, comm. 5v, 66mhz x x -icuil ssop24, stick & dry pack, ind. 2.7-5.5v, 40 mhz x x -icfcl ssop24, tape & reel & dry pack, comm. 2.7-5.5v, 40 mhz x x -icfcv ssop24, tape & reel & dry pack, comm. 5v, 66mhz x x -icfil ssop24, tape & reel & dry pack, ind. 2.7-5.5v, 40 mhz x x -3zsel engineering sample, dil24, stick, 2.7-5.5v, 40mhz x -tdsel engineering sample, so24, stick, 2.7-5.5v, 40mhz x czsel engineering sample, ceramic windowed dil24, stick, 2.7-5.5v, 40mhz x |
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